Phase-locked-loop (PLL) applications typically provide a synchronous output clock signal by comparing it to a reference clock signal. A phase-frequency detector (PFD) circuit is often employed to provide an analog control signal to a loop filter. The PFD circuit provides the control signal in response to a comparison of the phase and frequency of the output clock signal to the reference clock signal. A voltage-controlled oscillator (VCO) is arranged to receive its control signal from the loop filter. The VCO produces the clock signal in response to the control signal such that the frequency of the clock is varied until its phase and frequency are matched to the reference clock signal.
Another technique often used in communication systems to provide frequency lock to a reference signal is the quadricorrelator, or a frequency detector. FIG. 1 is a block diagram of an exemplary topology, illustrating the functioning of the quadricorrelator, which includes three mixers 103, 105 and 117, two low-pass filters 111 and 113, a differentiator 115, and a reference clock generator 109 with a ninety degree phase shifter 107 to generate the in-phase and quadrature reference clocks. The input signal, SIN(wit) is multiplied with the in-phase and quadrature reference clocks, SIN(wREFt) and COS(wREFt), via the mixers 103 and 105 to generate the corresponding in-phase and quadrature baseband components. The low-pass filters 111 and 113 suppress the unwanted component wi+wREF and pass the wi−wREF component. The in-phase component is differentiated by 115 and multiplied with the quadrature component via the mixer 117 to generate an analog voltage that is proportional to the difference between the input frequency and the reference frequency. However, the quadricorrelator has a limited frequency capture range, and is not suitable in many oscillator tuning circuits.
A phase-frequency detector (PFD) as illustrated in FIG. 2 is capable of both locking the phase and frequency of the input clock to a reference clock. The PFD comprises two flip-flops 205 and 209, and an AND logic gate 207. It provides UP and DOWN signals in response to a comparison between the input clock signal and the reference clock signal. The UP signal is active when the frequency of the input clock signal is low, while the DOWN signal is active when the frequency of the input clock signal is high. Similarly, the UP signal is active when the phase of the input clock is lagging behind the phase of the reference clock, and the DOWN signal is active when the phase of the input clock is leading the phase of the reference clock. The PFD has a much wider frequency capture range as compared to the quadricorrelator, and has been widely used in modern phase-locked loop applications. However, the PFD does not provide instantaneous true frequency detection, since only the average of the UP and DOWN signals can provide the frequency detection over time.